View EL911508_4138779.PDF datasheet online --- IC-ON-LINE

Datasheet File OCR Text:

(R)
EL9115
Data Sheet February 8, 2008 FN7441.4
Triple Analog Video Delay Line
The EL9115 is a triple analog delay line that allows skew compensation between any three signals. This part is perfect for compensating for the skew introduced by a typical CAT-5 cable with differing electrical lengths on each pair. The EL9115 can be programmed in steps of 2ns up to 62ns total delay on each channel.
Features
* 62ns total delay * 2ns delay step increments * Operates from 5V supply * Up to 122MHz bandwidth * Low power consumption * 20 Ld QFN (5mmx5mm) package
PKG. DWG. #
Ordering Information
PART NUMBER EL9115IL EL9115IL-T7* PART MARKING 9115IL 9115IL PACKAGE
* Pb-free available (RoHS compliant)
20 Ld 5mmx5mm QFN L20.5x5C 20 Ld 5mmx5mm QFN L20.5x5C 20 Ld 5mmx5mm QFN L20.5x5C 20 Ld 5mmx5mm QFN L20.5x5C (Pb-free) 20 Ld 5mmx5mm QFN L20.5x5C (Pb-free) 20 Ld 5mmx5mm QFN L20.5x5C (Pb-free)
Applications
* Skew control for RGB * Analog beamforming
EL9115IL-T13* 9115IL EL9115ILZ (Note) 9115ILZ
Pinout
EL9115 (20 LD 5X5 QFN) TOP VIEW
18 TESTG 19 TESTR 17 TESTB 16 VSPO 15 ROUT 14 GNDO THERMAL PAD 13 GOUT 12 VSMO 11 BOUT CENABLE 7 NSENABLE 8 SCLOCK 10 BIN 6 SDATA 9
EL9115ILZ-T7* 9115ILZ (Note) EL9115ILZ-T13* 9115ILZ (Note)
*Please refer to TB347 for details on reel specifications. NOTE: These Intersil Pb-free plastic packaged products employ special Pb-free material sets; molding compounds/die attach materials and 100% matte tin plate PLUS ANNEAL - e3 termination finish, which is RoHS compliant and compatible with both SnPb and Pb-free soldering operations. Intersil Pb-free products are MSL classified at Pb-free peak reflow temperatures that meet or exceed the Pb-free requirements of IPC/JEDEC J STD-020.
VSP 1 RIN 2 GND 3 GIN 4 VSM 5
EXPOSED DIEPLATE SHOULD BE CONNECTED TO -5V
1
CAUTION: These devices are sensitive to electrostatic discharge; follow proper IC Handling Procedures. 1-888-INTERSIL or 1-888-468-3774 | Intersil (and design) is a registered trademark of Intersil Americas Inc. Copyright Intersil Americas Inc. 2004-2006, 2008. All Rights Reserved All other trademarks mentioned are the property of their respective owners.
20 X2
EL9115
Absolute Maximum Ratings (TA = +25C)
Supply Voltage (VS+ to VS-) . . . . . . . . . . . . . . . . . . . . . . . . . . . .12V Maximum Output Current. . . . . . . . . . . . . . . . . . . . . . . . . . . . 60mA Storage Temperature Range . . . . . . . . . . . . . . . . . .-65C to +150C
Thermal Information
Pb-free reflow profile . . . . . . . . . . . . . . . . . . . . . . . . . .see link below http://www.intersil.com/pbfree/Pb-FreeReflow.asp
Operating Conditions
Operating Junction Temperature . . . . . . . . . . . . . . . . . . . . . . +135C Ambient Operating Temperature . . . . . . . . . . . . . . . .-40C to +85C
CAUTION: Do not operate at or near the maximum ratings listed for extended periods of time. Exposure to such conditions may adversely impact product reliability and result in failures not covered by warranty. IMPORTANT NOTE: All parameters having Min/Max specifications are guaranteed. Typical values are for information purposes only. Unless otherwise noted, all tests are at the specified temperature and are pulsed tests, therefore: TJ = TC = TA
DC Electrical Specifications
PARAMETER V+ VG_0 G_m G_f DG_m0 DG_f0 DG_fm VIN VOUT IB RIN VOS_0 VOS_M VOS_F ZOUT
VSA+ = VA+ = +5V, VSA- = VA- = -5V, TA = +25C, exposed die plate = -5V, unless otherwise specified. CONDITION MIN +4.5 -4.5 X2 = 5V, 150 load 1.81 1.66 1.52 -7.5 -13.5 -10.0 Gain falls to 90% of nominal X2 = +5V into 150 load -0.7 -5 1 10 X2 = +5V, 75 + 75 load -200 -200 -200 Chip enable = +5V Chip enable = 0V 4.5 -150 -140 -130 4.8 1 -38 -53 75 -10.5 -13 10 87 -8.6 -11.6 11.8 0.9 1.6 30 1.25 0.8 1.15 1.6 115 -7 -10 15.5 mA mA mA V V 60 60 60 5.1 1.89 1.84 1.79 -2.5 -6.0 -2.6 TYP MAX +5.5 -5.5 2.04 2.04 2.04 2.5 2.5 4.0 1.3 1.6 5 % % % V V A M mV mV mV M dB dB mA mA mA UNIT V V
DESCRIPTION Positive Supply Range Negative Supply Range Gain Zero Delay Gain Mid Delay Gain Full Delay Difference in Gain, 0 to Mid Difference in Gain, 0 to Full Difference in Gain, Mid to Full Input Voltage Range Output Voltage Range Input Bias Current Input Resistance Output Offset 0 Delay Output Offset Full Delay Output Offset Mid Delay Output Impedance
+PSRR -PSRR ISP ISM ISMO ISPO
ISP
Rejection of Positive Supply Rejection of Negative Supply Supply Current (Note 1) Supply Current (Note 1) Supply Current (Note 1) Supply Current (Note 1) Supply Current (Note 1) Supply Current (Note 1) Output Drive Current Logic High Logic Low
X2 = +5V into 75 + 75 load X2 = +5V into 75 + 75 load Chip enable = +5V current on VSP Chip enable = +5V current in VSM Chip enable = +5V current in VSMO Chip enable = +5V current in VSPO Increase in ISP per unit step in delay Chip enable = 0V current in VSP 10 load, 0.5V drive, X2 = 5V Switch high threshold Switch low threshold
ISP OFF IOUT LHI LLO NOTE:
1. All supply currents measured with Delay R = 0ns, G = mid delay, B = full delay.
2
FN7441.4 February 8, 2008
EL9115
AC Electrical Specifications
PARAMETER BW -3dB BW 0.1dB SR tR - t F VOVER Glitch THD Xt VN dt tMAX DELDT tPD tMAX t_en_ck 3dB Bandwidth 0.1dB Bandwidth Slew Rate Transient Response Time Voltage Overshoot Switching Glitch Total Harmonic Distortion Hostile Crosstalk Output Noise Delay Increment Maximum Delay Delay Diff Between Channels Propagation Delay Max s_clock Frequency Minimum Separation Between Serial Enable and Clock Measured input to output Maximum programming clock speed Check enable low edge can occur after t_en_ck of previous (ignored) clock and up to before t_en_ck of next (wanted) clock. Clock edges occurring within t_en_ck of the enable edge will have uncertain effect. 10 8.5 VSA+ = VA+ = +5V, VSA- = VA- = -5V, TA = +25C, exposed die plate = -5V, unless otherwise specified. CONDITION 0ns Delay Time 0ns Delay Time 0ns Delay Time 20% to 80%, for all delays, 1V step for any delay, response to 1V step input Time for o/p to settle after last s_clock edge 1VP-P 10MHz sinewave, offset by +0.2V at mid delay setting Stimulate G, measure R/B at 1MHz Gain X2, measured at 75 load 1.75 55 MIN TYP 122 60 400 2.5 5 100 -50 -80 2.5 2 62 1.6 9.8 11 10 2.25 70 -40 10 MAX UNIT MHz MHz V/s ns % ns dB dB mVRMS ns ns % ns MHz ns
DESCRIPTION
Pin Descriptions
PIN NUMBER 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 Thermal Pad PIN NAME VSP RIN GND GIN VSM BIN CENABLE NSENABLE SDATA SCLOCK BOUT VSMO GOUT GNDO ROUT VSPO TESTB TESTG TESTR X2 PIN DESCRIPTION +5V for delay circuitry and input amp Red channel input, ref GND 0V for delay circuitry supply Green channel input, ref GND -5V for input amp Blue channel input, ref GND Chip enable logical +5V enables chip ENABLE for serial input; enable on low Data into registers; logic threshold 1.2V Clock to enter data; logical; data written on negative edge Blue channel output, ref GNDO -5V for output buffers Green channel output, ref GNDO 0V reference for input and output buffers Red channel output, ref GNDO +5V for output buffers Blue channel phase detector output Green channel phase detector output Red channel phase detector output Sets gain to 2X if input high; X1 otherwise Must be connected to -5V
3
FN7441.4 February 8, 2008
EL9115 Typical Performance Curves
Delay = 0ns -3dB@122MHz
Delay = 0ns
Delay = 62ns
Delay = 62ns -3dB@80MHz Delay 10, 20, 30, 40 and 50ns
Delay 10, 20, 30, 40 and 50ns
FIGURE 1. GAIN vs FREQUENCY
FIGURE 2. GAIN vs FREQUENCY
DELAY TIME (ns)
DELAY TIME (ns) DELAY
FIGURE 3. TYPICAL DC OFFSET vs DELAY TIME (X2 = Hi)
FIGURE 4. TYPICAL DC OFFSET vs DELAY TIME (X2 = Low)
DELAY TIME (ns)
DELAY TIME (ns)
FIGURE 5. RISE TIME vs DELAY TIME
FIGURE 6. FALL TIME vs DELAY TIME
4
FN7441.4 February 8, 2008
EL9115 Typical Performance Curves (Continued)
Vout = 1Vptp
3 Channels
DELAY TIME (ns)
FIGURE 7. DISTORTION vs FREQUENCY
FIGURE 8. POSITIVE SUPPLY CURRENT vs DELAY TIME
X2 Hi_62ns Delay
X2 Hi_62ns Delay X2 Hi_0ns Delay X2 Low_62ns Delay
X2 Hi_0ns Delay X2 Low_62ns Delay
X2 Low_0ns Delay
X2 Low_0ns Delay
FIGURE 9. ISUPPLY+ vs VSUPPLY+
FIGURE 10. ISUPPLY- vs VSUPPLY-
1.2
POWER DISSIPATION (W)
JEDEC JESD51-3 LOW EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD
JEDEC JESD51-7 HIGH EFFECTIVE THERMAL CONDUCTIVITY TEST BOARD - QFN EXPOSED DIEPAD SOLDERED TO PCB PER JESD51-5 4.5 4.0
POWER DISSIPATION (W)
1.0 833mW 0.8
QF N2 15 0 0 C/ W
3.5 3.0 2.5 2.0 1.5 1.0 0.5 0
3.125W
QF N2 0 40 C /W
0.6 0.4 0.2 0 0 25
JA =
JA =
50
75 85 100
125
150
0
25
50
75 85 100
125
150
AMBIENT TEMPERATURE (C)
AMBIENT TEMPERATURE (C)
FIGURE 11. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
FIGURE 12. PACKAGE POWER DISSIPATION vs AMBIENT TEMPERATURE
5
FN7441.4 February 8, 2008
EL9115
1
VSP
19
TESTR
17
TESTB
18
TESTG
16
VSPO
CENABLE 7
2
R_IN
+
DELAY LINE + R_OUT 15
4
G_IN
+
DELAY LINE + G_OUT 13
6
B_IN
+
DELAY LINE + B_OUT 11 X2 20 CONTROL LOGIC
VSMO
9 10 8
SDATA SCLOCK NSENABLE
GND VSM
[BOTTOM PLATE] C
3
5
12
14
FIGURE 13. EL9115 BLOCK DIAGRAM
Applications Information
EL9115 is a triple analog delay line receiver that allows skew compensation between any three high frequency signals. This part compensates for time skew introduced by a typical CAT-5 cable with differing electrical lengths on each pair. The EL9115 can be independently programmed via SPI interface in steps of 2ns up to 62ns total delay on each channel while achieving over 80MHz bandwidth. Figure 13 shows the EL9115 block diagram. The 3 analog inputs are ground reference single-ended signals. After the signal is received, the delay is introduced by switching filter blocks into the signal path. Each filter block is an all-pass filter introducing 2ns delay. In addition to time delay, each filter block also introduces some low pass filtering. As a result, the bandwidth of the signal path decreases from 120MHz at 0ns delay setting to 80MHz at the maximum delay setting, as shown in Figure 1 of the "Typical Performance Curves" on page 4. In addition to delay, the extra amplifiers in the signal path also introduce offset voltage. The output offset voltage can shift by 100mV for X2 high setting and 50mV for X2 low. In operation, it is best to allocate the most delayed signal 0ns delay then increase the delay on the other channels to bring them into line. This will result in the lowest power and distortion solution to balancing delays.
Power Dissipation
As the delay setting increases, additional filter blocks turn on and insert into the signal path. For each 2ns of delay per channel, VSP current increases by 0.9mA while VSM does not change significantly. Under the extreme settings, the positive supply current reaches 140mA and the negative supply current can be 35mA. Operating at 5V power supply, the total power dissipation is:
PD = 5 * 140mA + 5 * 35mA = 875mW (EQ. 1)
JA required for long term reliable operation can be calculated. This is done using Equation 2:
JA = ( T J - T A ) PD = 57 C W (EQ. 2)
Where: TJ is the maximum junction temperature (+135C) TA is the maximum ambient temperature (+85C) For a 20 Ld package in a proper layout PCB heatsinking copper area, 40C/W JA thermal resistance can be achieved. To disperse the heat, the bottom heatspeader must be soldered to the PCB. Heat flows through the heatspreader to the circuit board copper then spreads and convects to air. Thus, the PCB copper plane becomes the heatsink (see TB389). This has proven to be a very effective technique. A separate application note, which details the 20 Ld QFN PCB design considerations, is available.
6
GND
FN7441.4 February 8, 2008
EL9115
TABLE 1. SERIAL BUS DATA vwxyz 00000 00001 00010 00011 00100 00101 00110 00111 01000 01001 01010 01011 01100 01101 01110 01111 10000 10001 10010 10011 10100 10101 10110 DELAY 0 2 4 6 8 10 12 14 16 18 20 22 24 26 28 30 32 34 36 38 40 42 44 TABLE 1. SERIAL BUS DATA (Continued) vwxyz 10111 11000 11001 11010 11011 11100 11101 11110 11111 DELAY 46 48 50 52 54 56 58 60 62
NOTE: Delay register word = 0abvwxyz; Red register - ab = 01; Green register - ab = 10; Blue register - ab = 11; vwxyz selects delay.
Serial Bus Operation
On the first negative clock edge after NSEnable goes low, read the input from DATA. This DATA level should be 0 (write into registers); READ is not supported. Read the next two data bits on subsequent negative edges and interpret them as the register to be filled. Reg 01 = R, 02 = G, 03 = B, 00 test use. Read the next five bits of data and send them to register. At the end of each block of 8 bits, any further data is treated as being a new word. Data entered is shifted directly to the final registers as it is clocked in. Initial value of all registers on power-up is 0. It is the user's responsibility to send complete patterns of 8 clock cycles, even if the first bit is set to 1. If less than 8 bits are sent, data will only be partially shifted through the registers. The pattern of 8 starts with NSEnable going low, so it is good practice to frame each word within an NS enable burst.
NSENABLE
SCLOCK
0
A1 a
A0 b
D4 v
D3 w
D2 x
D1 y
D0 z
SDATA
7
FN7441.4 February 8, 2008
EL9115
Test Pins
Three test pins are provided (Test R, Test G, Test B). During normal operation, the test pins output pulses of current for a duration of the overlap between the inputs, as shown in Figure 14: Test_R pulse = Red out (A) wrt Green out (B) Test_G pulse = Green out Test_B pulse = Blue out wrt Blue out wrt Red out
4 SLICING LEVEL A
B
OUTPUT
Averaging the current gives a direct measure of the delay between the two edges. When A precedes B the current pulse is +50A, and the output voltage goes up. When B precedes A, the pulse is -50A. For the logic to work correctly, A and B must have a period of overlap while they are high (a delay longer than the pulse width cannot be measured). Signals A and B are derived from the video input by comparing the video signal with a slicing level, which is set by an internal DAC. This enables the delay to be measured either from the rising edges of sync-like signals encoded on top of the video or from a dedicated set-up signal. The outputs can be used to set the correct delays for the signals received. The DAC level is set through the serial input by bits 1 through 4 directed to the test register (00).
VIDEO IN
COMPARATORS A
B
FIGURE 14. DELAY DETECTOR TABLE 2. wxyz 1000 1001 1010 1011 1100 DAC/mV -400 -350 -300 -250 -200 -150 -100 -50 0 50 100 150 200 250 300 350
Test Mode
Bit zero of the test register is set to 0 for normal operation. If it is set to 1 then the device is in Test Mode. In Test Mode, the DAC voltage is directed to the Green channel output, while for the Red and Blue channels, the test outputs are now pulses of current which are generated by looking at the delay between the input and output of the channel. They thus enable the delay to be measured.
1101 1110 1111 0000 0001 0010 0011 0100 0101 0110 0111
NOTE: Test Register word = 000wxyzt. If t = 1 test mode else normal. wxyz fed to DAC. z is LSB
8
FN7441.4 February 8, 2008
EL9115 Quad Flat No-Lead Plastic Package (QFN)
A N (N-1) (N-2) D B
L20.5x5C
20 LEAD QUAD FLAT NO-LEAD PLASTIC PACKAGE (COMPLIANT TO JEDEC MO-220) MILLIMETERS SYMBOL A A1 b c D MIN 0.80 0.00 0.28 NOMINAL 0.90 0.02 0.30 0.20 REF 5.00 BASIC 3.70 REF 5.00 BASIC 3.70 REF 0.65 BASIC 0.35 0.40 20 5 REF 5 REF 0.45 MAX 1.00 0.05 0.32 NOTES 8 8 4 6 5 Rev. 0 6/06
1 2 3
PIN #1 I.D. MARK
E
(2X) 0.075 C (N/2) 0.075 C TOP VIEW
D2 E E2 e L N ND NE
(2X)
C SEATING PLANE
e
0.10 C
0.08 C N LEADS AND EXPOSED PAD
SEE DETAIL "X" SIDE VIEW
NOTES: 1. Dimensioning and tolerancing per ASME Y14.5M-1994. 2. Tiebar view shown is a non-functional feature. 3. Bottom-side pin #1 I.D. is a diepad chamfer as shown. 4. N is the total number of terminals on the device.
0.01 M C A B
L N LEADS b (N-2) (N-1) N PIN #1 I.D.
5. NE is the number of terminals on the "E" side of the package (or Y-direction). 6. ND is the number of terminals on the "D" side of the package (or X-direction). ND = (N/2)-NE. 7. Inward end of terminal may be square or circular in shape with radius (b/2) as shown. 8. If two values are listed, multiple exposed pad options are available. Refer to device-specific datasheet. 9. One of 10 packages in MDP0046
3
1 2 3
(E2)
NE 5 (N/2)
(D2) BOTTOM VIEW
7
C
A
(c)
2
A1 DETAIL "X"
(L) N LEADS
All Intersil U.S. products are manufactured, assembled and tested utilizing ISO9000 quality systems. Intersil Corporation's quality certifications can be viewed at www.intersil.com/design/quality
Intersil products are sold by description only. Intersil Corporation reserves the right to make changes in circuit design, software and/or specifications at any time without notice. Accordingly, the reader is cautioned to verify that data sheets are current before placing orders. Information furnished by Intersil is believed to be accurate and reliable. However, no responsibility is assumed by Intersil or its subsidiaries for its use; nor for any infringements of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of Intersil or its subsidiaries.
For information regarding Intersil Corporation and its products, see www.intersil.com 9
FN7441.4 February 8, 2008

▲Up To Search▲

Price & Availability of EL911508

	To Download EL911508 Datasheet File
If you can't view the Datasheet, Please click here to try to view without PDF Reader .